1. Field of the Invention
The present invention generally relates to Integrated circuit structures and fabrication and, more particularly, to formation of wiring having improved resistance to electromigration and stress migration failure and high precision capacitors.
2. Description of the Prior Art
Increasing density of integrated circuits has been encouraged by both the economies to be derived from manufacture of more integrated circuits on each wafer and the performance benefits of decreased noise susceptibility and increased signal propagation speed. However, high integration density implies small feature size (e.g. interconnect line width) and decreased wiring pitch in-order to interconnect increased numbers of electronic elements formed on each chip.
While methods of depositing interconnection materials on wafers have become highly developed and can be performed with high manufacturing yield, connections, referred to as interconnects, formed at small sizes may fail after being put into service due to processes which occur within grains and grain boundaries of interconnect materials. Specifically, metal migration phenomena, known as electromigration and stress migration are principal causes of such failures. (The term xe2x80x9cmetal migrationxe2x80x9d is used hereinafter as generic to both stress migration failure and electromigration.)
Electromigration is an incident of drift, motion, transport, migration, or displacement of metal atoms caused by passage of an electric current through an interconnect. Electromigration phenomena are affected by interconnect structure such as composition, grain size, layering and film orientation texture. For this reason, for example, large grain metal deposition is favored for resistance of a single metal to electromigration. Metal migration causes an accumulation of metal atoms and a complementary formation of voids in the crystal lattice which may eventually lead to opening of the interconnect. The transport and piling-up of metal atoms may also cause the formation of so-called hillocks or extrusions which are localized increases in cross-sectional dimensions of the conductor. Such an increase in dimensions may cause an electrical short circuit to a nearby-conductor or breakage of adjacent structures such as cracking of insulators which constitute another but related failure mode of a chip.
Electromigration is enhanced at any point at which current density increases in a conductor such as at a notch, a void or a thinning of an interconnect. Electromigration thus tends to increase any irregularity in the formation of an interconnect and to accelerate over time. The principal mechanism of preventing electromigration has been to decrease current density in the electronic design of the integrated circuit which, of course, imposes a trade-off between circuit reliability and both performance (if current density is reduced by reduction of signal levels) and integration density (if current density is reduced by increased interconnect dimensions).
Stress migration failure is also an incident of diffusion of metal atoms and is principally due to thermally induced stress. Specifically, while increase of temperature may tend to reduce stress in a semiconductor device, subsequent cooling increases stress while the device remains at a relatively high temperature allowing some relief of stress through material movement. A net migration of metal atoms can eventually cause opening of a conductor in the same manner as electromigration. Further, even when integrated circuits are carefully designed with cautious observance of current density levels in design and close tolerances in manufacture, the effects of stress-induced void formation can exacerbate electromigration effects.
Different materials exhibit different levels of tendency toward electromigration and stress migration failure. Aluminum, although very desirable in regard to most of its other properties, particularly as to cost, exhibits both electromigration and stress migration failure under common use and processing conditions. Therefore, substantial efforts have been made to increase the reliability of conductors by choice and combination of materials, particularly in regard to interconnect structures including aluminum. Layered interconnects have been of particular interest for such a purpose and are often referred to as redundant wiring structures since non-aluminum conductors can reduce the current density in the aluminum but remain available should the aluminum layer open. Other layers can, however be broken by hillock or extrusion formation on the aluminum layer.
For example, a so-called hafnium sandwich structure is known and has shown particular promise by reducing electromigration and median time to failure, thereby increasing circuit reliability. In this structure, a thin layer of hafnium is deposited on an aluminum layer and a further aluminum layer deposited thereover. Then, the aluminum and hafnium are reacted to form hafnium tri-aluminide (HfAl3) at the interfaces. This structure provides a stable, dense barrier which prevents diffusion of aluminum between aluminum layers and the coincidence of voids or opens which might eventually develop. This structure does not prevent electromigration within each aluminum layer but an open or near-open which eventually develops in one aluminum layer would be able to heal before an open in the other aluminum alloy layer would be caused by an increase in current density at the same location in the other aluminum alloy layer.
However, the xe2x80x9chafnium sandwichxe2x80x9d structure has additional unique problems and failure modes. Specifically, the formation of hafnium tri-aluminide is accompanied by a reduction of volume, causing void formation in the aluminum alloy. If the hafnium-aluminide is not completely formed prior to passivation, additional volume reduction may occur due to continuance of the reaction, further increasing stresses in surrounding structures and leading to defect formation. Formation of extrusions also occurs in the hafnium sandwich structure.
Other structures involving layers of metal and redundant conductors are also known and in use; some of which provide relative advantages as compared to others. Nevertheless, all known structures intended to reduce electromigration and/or stress migration failure have some failure modes.
As alluded to above, another failure mode of interconnections formed on integrated circuit chips is caused by severe topography over which a conductor is deposited. Further, severe topography can compromise the accuracy with which lithographic patterning can be carried out and may cause irregularity of conductor width and/or separation. Topography of sufficient severity to compromise conductor integrity may occur at any edge of any layer formed on the surface of the substrate or another layer such as a conductor crossing another conductor (and insulator) particularly if the layer is relatively thick or patterned in a manner to form a sharp angle with the surface of the substrate or other underlying layer, as may be required in many electronic elements.
Formation of capacitors in integrated circuits is generally well-known. Trench capacitor structures employed to save space in, for example, large dynamic memories, however, tend to exhibit variation in capacitance because of low carrier concentrations at interfaces of both capacitor plates. Another concern is the limited voltage which may be applied across the dielectric of a trench capacitor structure. While such a variation in capacitance and voltage limitation is generally tolerable in digital circuits, there are many types of analog circuits in which variation in capacitance with voltage is not tolerable and requires metal plates to increase carrier concentrations. The thickness of two metal plates and an intervening capacitor dielectric layer is generally sufficient to present severe topography and thus to compromise the integrity of conductors and other structures which may be formed thereover. Further, due to the difference in thickness of such a so-called metal-to-metal capacitor from the thickness of conductors and the presence of a capacitor dielectric required separate formation of capacitors and interconnect, particularly of the redundant conductor type, during the same processes or at the same level, compounding the complexities imposed by device topography (such as planarization for formation of subsequent overlying layers) and causing increased cost and reduction in manufacturing yield because of the required separate manufacturing processes. Moreover, when overlying structures are to be formed over a group of layers containing both interconnects and metal-to-metal capacitors, the number of layers involved in portions of the structure causes increased difficulty and expense in planarization of a passivation layer or inter-level dielectric structure.
It is therefore an object of the present invention to provide a metal conductor and metal-to-metal precision capacitor structure which is highly resistant to metal migration and can be formed with the same process.
It is another object of the invention to provide an interconnect structure and manufacturing process which permits simultaneous production of interconnects which are highly resistant to metal migration coplanar with high precision capacitors.
It is a further object of the invention to provide a semiconductor device structure in which a group of layers containing both interconnects and metal-to-metal capacitors allows planarization of an overlying passivation layer or inter-level dielectric to be readily and economically achieved.
In order to accomplish these and other objects of the invention, an electronic device is provided including an interconnect and a capacitor, both including respective portions of a first metal layer, a dielectric layer and a second metal layer, and further including a connection to both the first metal layer and the second metal layer of the interconnect and a connection to each of the first metal layer and the second metal layer of the capacitor.
In accordance with another aspect of the invention, a method of making an electronic device and an electronic device formed by the method is provided including the steps of depositing a first metal layer and a dielectric layer on a surface, patterning the first metal layer and the dielectric layer to form a first aperture, depositing a second metal layer on the dielectric layer, patterning the second metal layer to form a second aperture overlying the first aperture, and connecting the first metal layer and the second metal layer at an edge of the second aperture.